This application relates to Dynamic Ramdon Access Memory (DRAM) cell for integrated circuits (IC), in particular the storage capacitor for the DRAM cell.
In a DRAM cell, it is desirable to reduce the size of a memory cell for increasing the memory capacity of an IC. Yet, the storage capacitance of the cell should be made large to increase charge storage. The requirements for small size and large storage capacitance are inconsistent.
To overcome the problem, various non-planar structures have been proposed. For instance, there have been proposed the sidewall capacitor structure as disclosed in U.S. Pat. No. 4,958,318, the stacked capacitor structure as disclosed in U.S. Pat. No. 5,413,950, etc. All these structures suffer from the lack of surface planarity and complicated processing, both of which reduce the production yield.
To overcome the planarity problems, a tunnel-shaped structure as disclosed in U.S. Pat. No. 5,262,663 has been proposed. The storage capacitor electrodes and the memory cell outlines are laid out in parallel, but such a layout sets a limit to the capacitance value as the capacitor electrode can be no longer than either the x-dimension or y-dimension of the memory cell.